
Intel listed total 28 commits that need us to back port. There are 9 commits that are already included in our code base. The commit "ice: Add support for E825-C TS PLL handling" will not be back ported since we're not dealing with E825 for 24.09. So we need back port 18 commits. These commits were introduced in linux-6.9.y and linux-6.10.y. To back port these 18 commits successfully, we totally back ported 37 upstream commits. 1) The patches 1-15 are cherry picked to fix the conflicts for patch 16 ("ice: introduce PTP state machine") and patch 36 "ice: Introduce ice_ptp_hw struct". Also will be helpful for the subsequent commits back porting. 2) The patches 24-27 are cherry picked to fix the conflicts for patch 28 ("ice: Fix debugfs with devlink reload") 3) The minor adjust was done for the patches 17, 21, 23 and 33 to fit with the context change. Verification: - installs from iso succeed on servers with ice(Intel Ethernet Controller E810-XXVDA4T Westport Channel) and i40e hw(Intel Ethernet Controller X710) for rt and std. - interfaces are up and pass packets for rt and std. - create vfs, ensure that they are picked up by the new iavf driver and that the interface can come up and pass packets on rt and std system. - Check dmesg to see DDP package is loaded successfully and the version is 1.3.36.0 for rt and std. Story: 2011056 Task: 50950 Change-Id: I9aef0378ea01451684341093a167eaead3edc458 Signed-off-by: Jiping Ma <jiping.ma2@windriver.com>
275 lines
8.7 KiB
Diff
275 lines
8.7 KiB
Diff
From e53280c20bbe58015a91178268244d5e831276f4 Mon Sep 17 00:00:00 2001
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From: Milena Olech <milena.olech@intel.com>
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Date: Tue, 2 Jul 2024 10:14:54 -0700
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Subject: [PATCH 34/36] ice: Fix improper extts handling
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Extts events are disabled and enabled by the application ts2phc.
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However, in case where the driver is removed when the application is
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running, a specific extts event remains enabled and can cause a kernel
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crash.
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As a side effect, when the driver is reloaded and application is started
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again, remaining extts event for the channel from a previous run will
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keep firing and the message "extts on unexpected channel" might be
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printed to the user.
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To avoid that, extts events shall be disabled when PTP is released.
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Fixes: 172db5f91d5f ("ice: add support for auxiliary input/output pins")
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Reviewed-by: Przemek Kitszel <przemyslaw.kitszel@intel.com>
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Co-developed-by: Jacob Keller <jacob.e.keller@intel.com>
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Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
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Signed-off-by: Milena Olech <milena.olech@intel.com>
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Signed-off-by: Karol Kolacinski <karol.kolacinski@intel.com>
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Reviewed-by: Simon Horman <horms@kernel.org>
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Tested-by: Pucha Himasekhar Reddy <himasekharx.reddy.pucha@intel.com> (A Contingent worker at Intel)
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Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
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Link: https://patch.msgid.link/20240702171459.2606611-2-anthony.l.nguyen@intel.com
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Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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(cherry picked from commit 00d3b4f54582d4e4a02cda5886bb336eeab268cc)
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Signed-off-by: Jiping Ma <jiping.ma2@windriver.com>
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---
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drivers/net/ethernet/intel/ice/ice_ptp.c | 105 ++++++++++++++++++-----
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drivers/net/ethernet/intel/ice/ice_ptp.h | 8 ++
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2 files changed, 91 insertions(+), 22 deletions(-)
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diff --git a/drivers/net/ethernet/intel/ice/ice_ptp.c b/drivers/net/ethernet/intel/ice/ice_ptp.c
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index 48ec59fc5d87..6e06c5d596b9 100644
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--- a/drivers/net/ethernet/intel/ice/ice_ptp.c
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+++ b/drivers/net/ethernet/intel/ice/ice_ptp.c
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@@ -1603,27 +1603,24 @@ void ice_ptp_extts_event(struct ice_pf *pf)
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/**
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* ice_ptp_cfg_extts - Configure EXTTS pin and channel
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* @pf: Board private structure
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- * @ena: true to enable; false to disable
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* @chan: GPIO channel (0-3)
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- * @gpio_pin: GPIO pin
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- * @extts_flags: request flags from the ptp_extts_request.flags
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+ * @config: desired EXTTS configuration.
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+ * @store: If set to true, the values will be stored
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+ *
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+ * Configure an external timestamp event on the requested channel.
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*/
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-static int
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-ice_ptp_cfg_extts(struct ice_pf *pf, bool ena, unsigned int chan, u32 gpio_pin,
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- unsigned int extts_flags)
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+static void ice_ptp_cfg_extts(struct ice_pf *pf, unsigned int chan,
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+ struct ice_extts_channel *config, bool store)
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{
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u32 func, aux_reg, gpio_reg, irq_reg;
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struct ice_hw *hw = &pf->hw;
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u8 tmr_idx;
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- if (chan > (unsigned int)pf->ptp.info.n_ext_ts)
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- return -EINVAL;
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-
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tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
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irq_reg = rd32(hw, PFINT_OICR_ENA);
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- if (ena) {
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+ if (config->ena) {
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/* Enable the interrupt */
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irq_reg |= PFINT_OICR_TSYN_EVNT_M;
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aux_reg = GLTSYN_AUX_IN_0_INT_ENA_M;
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@@ -1632,9 +1629,9 @@ ice_ptp_cfg_extts(struct ice_pf *pf, bool ena, unsigned int chan, u32 gpio_pin,
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#define GLTSYN_AUX_IN_0_EVNTLVL_FALLING_EDGE BIT(1)
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/* set event level to requested edge */
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- if (extts_flags & PTP_FALLING_EDGE)
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+ if (config->flags & PTP_FALLING_EDGE)
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aux_reg |= GLTSYN_AUX_IN_0_EVNTLVL_FALLING_EDGE;
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- if (extts_flags & PTP_RISING_EDGE)
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+ if (config->flags & PTP_RISING_EDGE)
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aux_reg |= GLTSYN_AUX_IN_0_EVNTLVL_RISING_EDGE;
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/* Write GPIO CTL reg.
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@@ -1656,9 +1653,47 @@ ice_ptp_cfg_extts(struct ice_pf *pf, bool ena, unsigned int chan, u32 gpio_pin,
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wr32(hw, PFINT_OICR_ENA, irq_reg);
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wr32(hw, GLTSYN_AUX_IN(chan, tmr_idx), aux_reg);
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- wr32(hw, GLGEN_GPIO_CTL(gpio_pin), gpio_reg);
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+ wr32(hw, GLGEN_GPIO_CTL(config->gpio_pin), gpio_reg);
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- return 0;
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+ if (store)
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+ memcpy(&pf->ptp.extts_channels[chan], config, sizeof(*config));
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+}
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+
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+/**
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+ * ice_ptp_disable_all_extts - Disable all EXTTS channels
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+ * @pf: Board private structure
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+ */
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+static void ice_ptp_disable_all_extts(struct ice_pf *pf)
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+{
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+ struct ice_extts_channel extts_cfg = {};
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+ int i;
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+
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+ for (i = 0; i < pf->ptp.info.n_ext_ts; i++) {
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+ if (pf->ptp.extts_channels[i].ena) {
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+ extts_cfg.gpio_pin = pf->ptp.extts_channels[i].gpio_pin;
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+ extts_cfg.ena = false;
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+ ice_ptp_cfg_extts(pf, i, &extts_cfg, false);
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+ }
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+ }
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+
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+ synchronize_irq(pf->oicr_irq.virq);
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+}
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+
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+/**
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+ * ice_ptp_enable_all_extts - Enable all EXTTS channels
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+ * @pf: Board private structure
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+ *
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+ * Called during reset to restore user configuration.
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+ */
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+static void ice_ptp_enable_all_extts(struct ice_pf *pf)
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+{
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+ int i;
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+
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+ for (i = 0; i < pf->ptp.info.n_ext_ts; i++) {
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+ if (pf->ptp.extts_channels[i].ena)
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+ ice_ptp_cfg_extts(pf, i, &pf->ptp.extts_channels[i],
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+ false);
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+ }
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}
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/**
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@@ -1815,7 +1850,6 @@ ice_ptp_gpio_enable_e810(struct ptp_clock_info *info,
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struct ptp_clock_request *rq, int on)
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{
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struct ice_pf *pf = ptp_info_to_pf(info);
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- struct ice_perout_channel clk_cfg = {0};
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bool sma_pres = false;
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unsigned int chan;
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u32 gpio_pin;
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@@ -1826,6 +1860,9 @@ ice_ptp_gpio_enable_e810(struct ptp_clock_info *info,
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switch (rq->type) {
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case PTP_CLK_REQ_PEROUT:
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+ {
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+ struct ice_perout_channel clk_cfg = {};
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+
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chan = rq->perout.index;
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if (sma_pres) {
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if (chan == ice_pin_desc_e810t[SMA1].chan)
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@@ -1853,7 +1890,11 @@ ice_ptp_gpio_enable_e810(struct ptp_clock_info *info,
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err = ice_ptp_cfg_clkout(pf, chan, &clk_cfg, true);
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break;
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+ }
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case PTP_CLK_REQ_EXTTS:
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+ {
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+ struct ice_extts_channel extts_cfg = {};
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+
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chan = rq->extts.index;
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if (sma_pres) {
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if (chan < ice_pin_desc_e810t[SMA2].chan)
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@@ -1869,9 +1910,13 @@ ice_ptp_gpio_enable_e810(struct ptp_clock_info *info,
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gpio_pin = chan;
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}
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- err = ice_ptp_cfg_extts(pf, !!on, chan, gpio_pin,
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- rq->extts.flags);
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- break;
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+ extts_cfg.flags = rq->extts.flags;
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+ extts_cfg.gpio_pin = gpio_pin;
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+ extts_cfg.ena = !!on;
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+
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+ ice_ptp_cfg_extts(pf, chan, &extts_cfg, true);
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+ return 0;
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+ }
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default:
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return -EOPNOTSUPP;
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}
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@@ -1889,21 +1934,31 @@ static int ice_ptp_gpio_enable_e823(struct ptp_clock_info *info,
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struct ptp_clock_request *rq, int on)
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{
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struct ice_pf *pf = ptp_info_to_pf(info);
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- struct ice_perout_channel clk_cfg = {0};
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int err;
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switch (rq->type) {
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case PTP_CLK_REQ_PPS:
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+ {
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+ struct ice_perout_channel clk_cfg = {};
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+
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clk_cfg.gpio_pin = PPS_PIN_INDEX;
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clk_cfg.period = NSEC_PER_SEC;
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clk_cfg.ena = !!on;
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err = ice_ptp_cfg_clkout(pf, PPS_CLK_GEN_CHAN, &clk_cfg, true);
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break;
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+ }
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case PTP_CLK_REQ_EXTTS:
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- err = ice_ptp_cfg_extts(pf, !!on, rq->extts.index,
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- TIME_SYNC_PIN_INDEX, rq->extts.flags);
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- break;
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+ {
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+ struct ice_extts_channel extts_cfg = {};
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+
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+ extts_cfg.flags = rq->extts.flags;
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+ extts_cfg.gpio_pin = TIME_SYNC_PIN_INDEX;
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+ extts_cfg.ena = !!on;
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+
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+ ice_ptp_cfg_extts(pf, rq->extts.index, &extts_cfg, true);
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+ return 0;
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+ }
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default:
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return -EOPNOTSUPP;
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}
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@@ -2735,6 +2790,10 @@ static int ice_ptp_rebuild_owner(struct ice_pf *pf)
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ice_ptp_restart_all_phy(pf);
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}
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+ /* Re-enable all periodic outputs and external timestamp events */
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+ ice_ptp_enable_all_clkout(pf);
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+ ice_ptp_enable_all_extts(pf);
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+
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return 0;
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}
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@@ -3286,6 +3345,8 @@ void ice_ptp_release(struct ice_pf *pf)
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ice_ptp_release_tx_tracker(pf, &pf->ptp.port.tx);
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+ ice_ptp_disable_all_extts(pf);
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+
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kthread_cancel_delayed_work_sync(&pf->ptp.work);
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ice_ptp_port_phy_stop(&pf->ptp.port);
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diff --git a/drivers/net/ethernet/intel/ice/ice_ptp.h b/drivers/net/ethernet/intel/ice/ice_ptp.h
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index 352405a2daf2..c6469a5a7afb 100644
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--- a/drivers/net/ethernet/intel/ice/ice_ptp.h
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+++ b/drivers/net/ethernet/intel/ice/ice_ptp.h
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@@ -33,6 +33,12 @@ struct ice_perout_channel {
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u64 start_time;
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};
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+struct ice_extts_channel {
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+ bool ena;
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+ u32 gpio_pin;
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+ u32 flags;
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+};
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+
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/* The ice hardware captures Tx hardware timestamps in the PHY. The timestamp
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* is stored in a buffer of registers. Depending on the specific hardware,
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* this buffer might be shared across multiple PHY ports.
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@@ -226,6 +232,7 @@ enum ice_ptp_state {
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* @ext_ts_irq: the external timestamp IRQ in use
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* @kworker: kwork thread for handling periodic work
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* @perout_channels: periodic output data
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+ * @extts_channels: channels for external timestamps
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* @info: structure defining PTP hardware capabilities
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* @clock: pointer to registered PTP clock device
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* @tstamp_config: hardware timestamping configuration
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@@ -249,6 +256,7 @@ struct ice_ptp {
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u8 ext_ts_irq;
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struct kthread_worker *kworker;
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struct ice_perout_channel perout_channels[GLTSYN_TGT_H_IDX_MAX];
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+ struct ice_extts_channel extts_channels[GLTSYN_TGT_H_IDX_MAX];
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struct ptp_clock_info info;
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struct ptp_clock *clock;
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struct hwtstamp_config tstamp_config;
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--
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2.43.0
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