853c60e2e8
This commit back ports the DPLL related commits from the upstream
kernel that are identified by Intel to provide the expected
SyncE/GNSS functionality.
There are totally 46 back ported commits included the four commits
I added are used to resolve the conflicts during back porting.
The 0046 patch is cherry picked from kernel-6.9.
The 0031-0045 patches are cherry picked from kernel-6.8.
The 0001-0030 patches are cherry picked from kernel-6.7.
We also change the in-tree ice driver version to 6.6.40-stx.2 from
6.6.40-stx.1.
* To fix the conflict of 91e43ca0090b ("ice: fix linking when
CONFIG_PTP_1588_CLOCK=n"), we cherry pick 12a5a28b565b
("ice: remove ICE_F_PTP_EXTTS feature flag") and 89776a6a702e
("ice: check netlist before enabling ICE_F_GNSS").
Adjust 12a5a28b565b because 0d1b22367ec2 ("ice: fix pin
assignment for E810-T without SMA control") already included
the part code of 12a5a28b565b.
https://git.yoctoproject.org/linux-yocto/commit/?id=0d1b22367ec2
* Cherry pick 7049fd5df7 ("netlink: specs: remove redundant type keys
from attributes in subsets") to fix the the conflict of c3c6ab95c397
("dpll: spec: add support for pin-dpll signal phase offset/adjust.")
* Cherry pick be16574609f1 ("ice: introduce hw->phy_model for handling
PTP PHY differences") to fix the confilict of 6db5f2cd9ebb ("ice:
dpll:fix output pin capabilities").
Verification:
- Build kernel and out of tree modules success for rt and std.
- Install success onto a All-in-One lab with rt kernel.
- Boot up successfully in the lab.
- interfaces are up and pass packets for rt and std.
- Check dmesg to see DDP package is loaded successfully and
the version is 1.3.36.0 for rt and std, that is same with the OOT
ice-1.14.9 driver.
- The SyncE/GNSS functionality tests were done by the network team.
Story: 2011056
Task: 50797
Change-Id: I715480681c7c43d53b0a0126b34135562e9d02a0
Signed-off-by: Jiping Ma <jiping.ma2@windriver.com>
175 lines
5.9 KiB
Diff
175 lines
5.9 KiB
Diff
From 304d5b650378394e20c1f65af6a4898c49f95e12 Mon Sep 17 00:00:00 2001
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From: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
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Date: Wed, 11 Oct 2023 12:12:33 +0200
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Subject: [PATCH 22/46] dpll: spec: add support for pin-dpll signal phase
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offset/adjust
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Add attributes for providing the user with:
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- measurement of signals phase offset between pin and dpll
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- ability to adjust the phase of pin signal
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Signed-off-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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(cherry picked from commit c3c6ab95c397134bf5948f18743b3ba8008e7c47)
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Signed-off-by: Jiping Ma <jiping.ma2@windriver.com>
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---
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Documentation/netlink/specs/dpll.yaml | 30 +++++++++++++++++++++++++++
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drivers/dpll/dpll_nl.c | 8 ++++---
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drivers/dpll/dpll_nl.h | 2 +-
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include/uapi/linux/dpll.h | 6 ++++++
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4 files changed, 42 insertions(+), 4 deletions(-)
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diff --git a/Documentation/netlink/specs/dpll.yaml b/Documentation/netlink/specs/dpll.yaml
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index 1c1b53136c7b..cf8abe1c0550 100644
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--- a/Documentation/netlink/specs/dpll.yaml
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+++ b/Documentation/netlink/specs/dpll.yaml
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@@ -164,6 +164,18 @@ definitions:
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-
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name: state-can-change
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doc: pin state can be changed
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+ -
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+ type: const
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+ name: phase-offset-divider
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+ value: 1000
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+ doc: |
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+ phase offset divider allows userspace to calculate a value of
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+ measured signal phase difference between a pin and dpll device
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+ as a fractional value with three digit decimal precision.
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+ Value of (DPLL_A_PHASE_OFFSET / DPLL_PHASE_OFFSET_DIVIDER) is an
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+ integer part of a measured phase offset value.
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+ Value of (DPLL_A_PHASE_OFFSET % DPLL_PHASE_OFFSET_DIVIDER) is a
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+ fractional part of a measured phase offset value.
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attribute-sets:
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-
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@@ -272,6 +284,18 @@ attribute-sets:
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type: nest
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multi-attr: true
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nested-attributes: pin-parent-pin
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+ -
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+ name: phase-adjust-min
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+ type: s32
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+ -
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+ name: phase-adjust-max
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+ type: s32
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+ -
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+ name: phase-adjust
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+ type: s32
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+ -
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+ name: phase-offset
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+ type: s64
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-
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name: pin-parent-device
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subset-of: pin
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@@ -284,6 +308,8 @@ attribute-sets:
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name: prio
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-
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name: state
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+ -
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+ name: phase-offset
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-
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name: pin-parent-pin
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subset-of: pin
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@@ -431,6 +457,9 @@ operations:
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- capabilities
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- parent-device
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- parent-pin
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+ - phase-adjust-min
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+ - phase-adjust-max
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+ - phase-adjust
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dump:
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pre: dpll-lock-dumpit
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@@ -458,6 +487,7 @@ operations:
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- state
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- parent-device
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- parent-pin
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+ - phase-adjust
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-
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name: pin-create-ntf
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doc: Notification about pin appearing
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diff --git a/drivers/dpll/dpll_nl.c b/drivers/dpll/dpll_nl.c
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index 14064c8c783b..eaee5be7aa64 100644
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--- a/drivers/dpll/dpll_nl.c
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+++ b/drivers/dpll/dpll_nl.c
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@@ -11,11 +11,12 @@
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#include <uapi/linux/dpll.h>
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/* Common nested types */
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-const struct nla_policy dpll_pin_parent_device_nl_policy[DPLL_A_PIN_STATE + 1] = {
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+const struct nla_policy dpll_pin_parent_device_nl_policy[DPLL_A_PIN_PHASE_OFFSET + 1] = {
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[DPLL_A_PIN_PARENT_ID] = { .type = NLA_U32, },
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[DPLL_A_PIN_DIRECTION] = NLA_POLICY_RANGE(NLA_U32, 1, 2),
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[DPLL_A_PIN_PRIO] = { .type = NLA_U32, },
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[DPLL_A_PIN_STATE] = NLA_POLICY_RANGE(NLA_U32, 1, 3),
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+ [DPLL_A_PIN_PHASE_OFFSET] = { .type = NLA_S64, },
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};
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const struct nla_policy dpll_pin_parent_pin_nl_policy[DPLL_A_PIN_STATE + 1] = {
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@@ -61,7 +62,7 @@ static const struct nla_policy dpll_pin_get_dump_nl_policy[DPLL_A_PIN_ID + 1] =
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};
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/* DPLL_CMD_PIN_SET - do */
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-static const struct nla_policy dpll_pin_set_nl_policy[DPLL_A_PIN_PARENT_PIN + 1] = {
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+static const struct nla_policy dpll_pin_set_nl_policy[DPLL_A_PIN_PHASE_ADJUST + 1] = {
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[DPLL_A_PIN_ID] = { .type = NLA_U32, },
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[DPLL_A_PIN_FREQUENCY] = { .type = NLA_U64, },
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[DPLL_A_PIN_DIRECTION] = NLA_POLICY_RANGE(NLA_U32, 1, 2),
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@@ -69,6 +70,7 @@ static const struct nla_policy dpll_pin_set_nl_policy[DPLL_A_PIN_PARENT_PIN + 1]
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[DPLL_A_PIN_STATE] = NLA_POLICY_RANGE(NLA_U32, 1, 3),
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[DPLL_A_PIN_PARENT_DEVICE] = NLA_POLICY_NESTED(dpll_pin_parent_device_nl_policy),
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[DPLL_A_PIN_PARENT_PIN] = NLA_POLICY_NESTED(dpll_pin_parent_pin_nl_policy),
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+ [DPLL_A_PIN_PHASE_ADJUST] = { .type = NLA_S32, },
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};
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/* Ops table for dpll */
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@@ -140,7 +142,7 @@ static const struct genl_split_ops dpll_nl_ops[] = {
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.doit = dpll_nl_pin_set_doit,
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.post_doit = dpll_pin_post_doit,
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.policy = dpll_pin_set_nl_policy,
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- .maxattr = DPLL_A_PIN_PARENT_PIN,
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+ .maxattr = DPLL_A_PIN_PHASE_ADJUST,
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.flags = GENL_ADMIN_PERM | GENL_CMD_CAP_DO,
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},
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};
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diff --git a/drivers/dpll/dpll_nl.h b/drivers/dpll/dpll_nl.h
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index 1f67aaed4742..92d4c9c4f788 100644
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--- a/drivers/dpll/dpll_nl.h
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+++ b/drivers/dpll/dpll_nl.h
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@@ -12,7 +12,7 @@
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#include <uapi/linux/dpll.h>
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/* Common nested types */
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-extern const struct nla_policy dpll_pin_parent_device_nl_policy[DPLL_A_PIN_STATE + 1];
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+extern const struct nla_policy dpll_pin_parent_device_nl_policy[DPLL_A_PIN_PHASE_OFFSET + 1];
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extern const struct nla_policy dpll_pin_parent_pin_nl_policy[DPLL_A_PIN_STATE + 1];
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int dpll_lock_doit(const struct genl_split_ops *ops, struct sk_buff *skb,
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diff --git a/include/uapi/linux/dpll.h b/include/uapi/linux/dpll.h
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index 20ef0718f8dc..715a491d2727 100644
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--- a/include/uapi/linux/dpll.h
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+++ b/include/uapi/linux/dpll.h
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@@ -138,6 +138,8 @@ enum dpll_pin_capabilities {
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DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE = 4,
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};
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+#define DPLL_PHASE_OFFSET_DIVIDER 1000
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+
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enum dpll_a {
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DPLL_A_ID = 1,
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DPLL_A_MODULE_NAME,
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@@ -173,6 +175,10 @@ enum dpll_a_pin {
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DPLL_A_PIN_CAPABILITIES,
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DPLL_A_PIN_PARENT_DEVICE,
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DPLL_A_PIN_PARENT_PIN,
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+ DPLL_A_PIN_PHASE_ADJUST_MIN,
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+ DPLL_A_PIN_PHASE_ADJUST_MAX,
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+ DPLL_A_PIN_PHASE_ADJUST,
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+ DPLL_A_PIN_PHASE_OFFSET,
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__DPLL_A_PIN_MAX,
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DPLL_A_PIN_MAX = (__DPLL_A_PIN_MAX - 1)
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--
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2.43.0
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